`timescale  1 ns/1 ps

module ${ip_name}_register #
(
    parameter               ${PARA1} = 128
)
(
    input   wire                csi_clk,
    input   wire                rsi_reset_n,

    input   wire [01:00]        avs_address,
    input   wire                avs_write,
    input   wire [31:00]        avs_writedata,
    output  reg  [${PARA1}-1:00]   coe_parameter_out
);

endmodule
